1. Field of the Invention
The present invention relates to a semiconductor package and a method for assembling the same.
2. Description of the Background Art
Generally, semi conductor packages are classified into two types of packages, that is, a plastic package type and a ceramic package type.
For clarifying an understanding of the present invention easy, methods for assembling the above-mentioned types of packages will now be described. A method for assembling the plastic type package will be first described.
First, a wafer 1 is subjected to a dicing so that it is divided into a plurality of chips 2, as shown in FIG. 1a. The dicing can be achieved by using a chemical method using acetic acid, fluoro acid or the like or a scribing method using-a diamond cutter. As shown in FIG. 1b, a lead frame 3 is also prepared. The lead frame 3 comprises a paddle 3a on which one of the chips 2 is laid, a plurality of inner leads 3b electrically connected with the chip 2 inwardly of the package, a plurality of outer leads 3c electrically connected with other elements outwardly of the package, a pair of spaced side rails 3d adapted to maintain the shape of the lead frame 3, dam bars 3e adapted to support the inner and outer leads 3b and 3c such that they are uniformly spaced between the side rails 3d, a pair of support bars 3f adapted to support the paddle 3a between the side rails 3d, and a plurality of locking holes 3g.
Thereafter, a die bonding is carried out for attaching the chip 2 to the paddle 3a, as shown in FIGS. 1c and 1d, FIG. 1d is a cross-sectional view taken along the line a--a' of FIG. 1c. Subsequently, a wire bonding is carried out for electrically connecting bonding pads 2a of the chip 2 with corresponding inner leads 3b by means of wires 4, as shown in FIG. 1e. The bonding pads 2a are generally formed on the surface of chip 2, so as to achieve the wire bonding as mentioned above. They are formed in a double line in case of a dual in line type package and in a single line in case of a single in line type package. The illustrated case corresponds to the dual in line type package.
The lead frame 3 which has been subjected to the die bonding and wire bonding is then positioned in a mold 5 having a mold cavity corresponding a desired shape of a package to be produced, as shown in FIG. 1f. Thereafter, an epoxy molding compound (EMC) 6 is charged into the mold cavity of the mold 5 and a molding is then carried out.
After molding, a trimming is carried out, for removing dam bars 3e from the molded package, as shown in FIG. 1g. Subsequently, a shaping process for shaping the outer leads 3c into a desired shape is performed as shown in FIG. 1h. In case shown in FIG. 1h, the outer leads 3c have a gull wing shape.
FIG. 11 shows the shape of a plastic package obtained by the above-mentioned method.
On the other hand, the ceramic package is used as a package for a charge coupled device (CCD) which is activated generally by receiving a light. The following is a method for assembling such a ceramic package.
First, a powder mixture is prepared by mixing a Al.sub.2 O.sub.3 compound with a proper additive. Using the powder mixture, several sheets are formed. On each sheet, is formed a metallic pattern for connecting leads with corresponding bonding pads of a chip which is to be laid on a lead frame. Thereafter, the sheets having desired metallic patterns are stacked over one another to form a multi-layered package structure having a desired shape as shown in FIG. 2a. The multi-layered package structure is then subjected to a sintering.
The multi-layered package structure shown fin FIG. 2a comprises three sheets, that, is, a bottom sheet 7, an intermediate sheet, 8 and a top sheet 9.
Thereafter, a die bonding is carried out, for attaching a chip 10 to a required position in the package, as shown in FIG. 2b. A wire bonding is then performed for electrically connecting the metallic patterns with bonding pads 10a of the chip 10 by means of wires 11, as shown in FIG. 2c.
As shown in FIG. 2d, a glass 12 is then covered over an opened area of the package. Subsequently, leads 13 are attached to required portions of opposite outside surfaces of the structure, as shown in FIG. 2e. Thus, a ceramic package is obtained, an inner structure of which is shown in FIG. 2f.
However, the above-mentioned methods for assembling a plastic package and assembling a ceramic package have the following problems.
In case of the plastic package, its manufacturing method is complex, even though the manufacture cost is inexpensive in that the plastic package is made from cheap materials. During the EMC molding following the wire bonding, the bonded wires are likely to be subjected to a sweeping phenomenon which causes them to be swept toward one side or to be broken. As a result, the rate of poor products becomes relatively high.
The method for assembling the ceramic package provides an advantage in case of making packages for semiconductor elements requiring a high precision, in that the ceramic package is made before the die bonding and wire bonding are carried out. However, it has a disadvantage of an expensive manufacture cost.
Moreover, recent technical developments in manufacture of semiconductor elements lead memory chips to be on an increasing trend in capacity. This trend also causes bare chips contained in semiconductor packages to increase in size. As a result, the occupied area of a bare chip in the overall area of the semi conductor package is on an increasing trend.
In addition to the above-mentioned disadvantage encountered in the plastic packages, the use of wires for electrically connecting a chip with leads in cases of the above-mentioned plastic and ceramic packages causes a problem that the packages increase in height and volume. This problem is contrary to efforts for making semiconductor packages light and thin.
As a technique for solving the above-mentioned problems, there has been known a lead on chip (LOC) technique wherein leads are directly connected to a chip, without using a wire bonding. Now, a method for assembling a small outline J (SOJ) type lead package according to the LOC technique will be described.
First, a lead frame is prepared for a LOC-SOJ package using a 16-mega-bit dynamic random access memory (16 M DRAM), as shown in FIG. 3a. In FIG. 3a, the reference numeral 14 is the lead frame, 14a a paddle on which a chip is laid, 14b inner leads, 14c outer leads, 14d dam bars, 14e side rails, 14f support bars, and 14g locking holes.
In this case, each inner lead 14b has the same thickness as that of each outer lead 14c and has a sufficient length so that, its free end can be laid on the upper surface of a chip which is laid on the paddle 14a.
Thereafter, a chip 15 which was previously prepared by dicing a wafer is laid on the paddle 14a of the lead frame 14 and then subjected to a die bonding for attaching the chip 15 to the paddle 14a, as shown in FIGS. 3b and 3c. An insulating layer 16 is coated over the upper surface of chip 15 except, for its portions corresponding to bonding pads 15a. FIG. 3c is a cross-sectional view taken along the line a--a'.
A wire bonding using wires 17 is then carried out for electrically connecting free ends of inner leads 14b with corresponding bonding pads of the chip 15, as shown in FIG. 3d.
Following the die bonding and wire bonding, a trimming is performed for removing dam bars 14d and support bars 14f. Thereafter, the lead frame 14 carrying the chip 15 is positioned in a mold 18. At this time, outer leads 14c of the lead frame 14 are positioned outwardly of the mold 18. An ENC 19 is charged into a mold cavity of the mold 18 and a molding is then carried out, as illustrated in FIG. 3e.
After molding, a shaping process for bending the outer leads 14c into a J-shape is performed as shown in FIG. 3f. Thus, a LOC-SOJ type package is obtained.
Such a LOC-SOJ type package has an advantage of providing a large area of inner leads occupied in the package, in that the inner leads 14b of the lead frame 14 extend to the upper surface of chip 15.
The inner leads 14b are also directly connected with the corresponding bonding pads 15a, without using wires. That is, each inner lead 14b is formed to have a sufficient length so that it can be directly connected with each corresponding bonding pad 15a of the chip 15. Each inner lead 14b is also coated at its free end with a bonding bumper 20, as shown in FIG. 4a. Each bonding bumper 20 is laid on each corresponding bonding pad 15a and then subjected to a heat pressing, so as to achieve an electrical connection between the inner leads 14b and the chip 15, as shown in FIG. 4b.
Subsequent processes are the same as those of FIG. 3 and thus their description and illustration are omitted.
However, the above-mentioned LOC-SOJ type package also has the following problems.
The volume of semiconductor package can be reduced by decreasing the height of a loop formed by each wire in the wire bonding. However, such a decrease in wire loop height may result in a problem that wires are broken. For preventing wires from being broken, it is required to change the material of wires or increase the diameter of wires. However, these methods are undesirable.
As a result, the semiconductor packages requiring wire bonding have the wire loop height higher than the height of inner leads, irrespective of the kind of wires used. Consequently, the height and volume of semiconductor packages increase.
Even in case of directly connecting the inner leads with the bonding pads by means of the bonding bumpers, the semiconductor package has a limitation in reducing its height, due to the thickness of inner leads.